1. Field of the Invention
The present invention generally relates to digital-to-analog converters, and more particularly, to a method of operating a multibit delta-sigma modulator in a digital-to-analog converter to enable smooth ramp-up when the digital-to-analog converter is first turned on.
2. Description of the Related Art
Digital-to-analog converters are used in a wide variety of digital signal processing (DSP) devices such as audio systems, programmable power supplies, and digitally controlled filters. A digital-to-analog converter is an electronic circuit that takes a digital input signal and uses logic elements to convert the digital signal into an analog output signal, which is further used to drive analog circuitry. For example, in an audio application, the analog output signal can be used to drive one or more speakers in a stereo system or alternatively a headphone of a portable music player such as an “MP3” player.
Early digital-to-analog converters (DACs) utilized resistive ladder networks, but most state-of-the-art DACs now utilize a “delta-sigma” modulator. A typical DAC 10 is illustrated in FIG. 1. A digital signal source 12 provides the primary input to the delta-sigma modulator 14. The digital signal source could be from, e.g., a digital radio receiver, an audio compact disc (CD), digital audio tape (DAT), a digital video disc (DVD) or a broadcast satellite. Delta-sigma modulator 14 feeds a multilevel noise-shaped signal based on the digital input stream to a back-end low-pass filter 18. This filter could be a discrete-time or continuous-time implementation. A continuous-time implementation may include a pulse-width modulation (PWM) encoder 16, which converts a multilevel delta-sigma output to one or more PWM bit streams. Low-pass filter 18 removes high frequencies from the output, and the filtered output then drives some other device such as a speaker 20.
A delta-sigma modulator is a circuit that translates a low-sample rate, high-resolution input into a high-sample rate, low-resolution output. This low-resolution output is then converted into a high-resolution analog signal by averaging it over time with the low-pass filter. The delta-sigma modulator generally involves two accumulator blocks in the circuit. The first block calculates the difference (delta) between two values (i.e., an error signal), and the second block accumulates the sum (sigma) of the error signal. Delta-sigma modulators are also useful in codec and similar mixed-signal applications.
A simplified delta-sigma modulator is shown in FIG. 2. The digital signal is a primary input into the delta accumulator 22, which further receives a feedback input. The output of delta accumulator 22 is the primary input to the sigma accumulator 24, which also receives a feedback input. The output of sigma accumulator 24 is fed to a latch 26, which is controlled by the clock signal. The output of latch 26 is an input to a quantizer 28 and is also the feedback input for accumulator 24. The purpose of the quantizer is to convert the high-resolution digital signal into a low-resolution representation, which can be accurately converted to an analog signal. The output of quantizer 28 is the output of delta-sigma modulator 14 and provides the input to the back-end filter.
The feedback loops in a delta-sigma modulator help reduce in-band quantization errors which cause distortion in the output signal. Oversampling is further employed with a delta-sigma modulator to spread the quantization noise power across an oversampling frequency band, which is typically much greater than the input signal bandwidth. Additionally, delta-sigma modulators perform noise shaping by acting as a high-pass filter to the noise such that most of the quantization noise power is shifted out of the signal band of interest. In a first order delta-sigma modulator, the linear filter comprises a single integrator stage, while the filter in a higher order modulator comprises a cascade of a corresponding number of integrator stages. Higher order modulators have the advantage of improved noise shaping capability over lower order modulators, but stability can become a problem as the order is increased.
During device power-up and power-down, a digital-to-analog system should produce no audible artifacts at its output. A problem, however, may exist for single-ended delta-sigma modulator DACs since the modulator cannot drive its output all the way to ground while remaining stable. It is possible to address this problem by driving the input of the delta-sigma modulator well below its nominal negative full-scale level, increasing the modulation index, and lowering the modulator order to maintain stability. The modulator input is then ramped from this low level to the common mode level, as discussed in U.S. Pat. No. 6,556,159 to Fei et al. entitled “Variable Order Modulator” which is incorporated by reference herein. Additionally, an analog gain stage can be used during ramp up to drive the output further toward ground. However, for DACs that utilize a PWM encoder as part of the back-end filter, constraints on the quantizer make this an incomplete solution.
These constraints relate to the requirement that a PWM system have an output stream with a constant edge rate. A system with a PWM encoder that does not have a constant edge rate will suffer from high distortion. For example, a PWM pulse width of eight clock cycles has nine possible values for this PWM pulse (0, 1, . . . 8) as shown in FIG. 2. However, to guarantee a constant edge rate (in this case, two edges per pulse), the first two cases (0,1) and last case (8) are not allowed, leaving only six allowed values for the pulse. If a delta-sigma quantizer is driving this PWM encoder, the quantizer is accordingly constrained to only those six legal values. This constraint on the quantizer output makes it difficult to achieve a high modulation index. PWM encoders are nevertheless desirable to use since the constant edge rate eliminates data dependent switching.
In light of the foregoing, it would be desirable to devise an improved delta-sigma modulator, which can take advantage of PWM encoding but still eliminate or reduce audible artifacts on power up. It would be further advantageous if a quantizer for such a delta-sigma modulator could be selectively modified to allow for a higher modulation index during ramp up.